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ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling rev. 03 ? 2 july 2012 product data sheet 1. general description the ADC1207S080 is a 12-bit analog-to-digit al converter (adc) optimized for direct input frequency (if) sampling and supporting the most demanding use conditions in ultra high if radio transceivers for cellular infrastructure and other applications such as wireless infrastructure, optical networking and fixed telecommunication. due to its broadband input capa bilities, the ADC1207S080 is ideal for single and mu ltiple carriers data conversion. operating at a maximum sampling rate of 80 mhz, analog input signals are converted into 12-bit binary coded digit al words. all static di gital inputs are cmos compatible. all output signals are low-voltage complementary metal-oxide semiconductor (lvcmos) compatible. the ADC1207S080 offers the mo st flexible acquisition control system because of its programmable complete conver sion signal (ccs) that allows to adjust the delay of the acquisition clock. the ADC1207S080 offers the lowest input capacitance (< 1 pf) and therefore the highest flexibility in front-end aliasing filter strategy because of its internal front-end buffer. 2. features ? 12-bit resolution ? dif ferential input with 375 mhz bandwidth ? 90 db sfdr; 71 db s/n (f i = 225 mhz; f clk = 80 mhz; b = 5 mhz) ? 74 db sfdr; 66.5 db s/n (f i = 175 mhz; f clk = 80 mhz; b = nyquist) ? hig h speed sampling rate up to 80 mhz ? in ternal front-end buffer (input capacitance < 1 pf) ? pr ogrammable acquisition output cl ock (complete conversion signal) ? full-scale controllable from 1.5 v to 2 v (p-p); continuous scale ? single 5 v power supply ? 3. 3 v lvcmos compatible digital outputs ? bina ry or two?s-complement lvcmos outputs ? cmos compatible st atic digital inputs ? only 2 clock cycles latency ? ind ustrial temperature range from ? 40 ? c to +85 ? c ? htqf p48 package
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 2 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling 3. applications high speed analog to digital conversion for: ? rad io transceivers ? wireless infrastruc ture ? ca ble modem ? digit al storage scope ? fixed t elecommunication, ? optic al networking ? wir eless local area networ k (wlan) infrastructure. ? gene ral purpose applications 4. ordering information table 1. ordering information type number package sampling frequency (mhz) name description version ADC1207S080hw htqfp48 plastic thermal enhanced thin quad flat package; 48 leads; body 7 ? 7 ? 1 mm; exposed die pad sot545-2 80 5. block diagram 12 12 2 014aaa430 track and hold adc core latch latch resistor ladders clock driver outputs enable cmadc reference vref reference ADC1207S080 u/i front-end buffer fsout inn fsin in del0 to del1 ccs d0 to d11 otc v cco ir dec cmadc clk clkn ce_n fig 1. block diagram
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 3 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling 6. pinning information 6.1 pinning ADC1207S080hw n.c. d0 agnd1 d1 in d2 cmadc d3 inn d4 agnd1 d5 dec d6 n.c. d7 fsout d8 fsin d9 n.c. d10 n.c. d11 dgnd n.c. agnd1 del1 v cca1 del0 agnd1 v ccd2 v cca1 dgnd2 v cca2 ce_n agnd2 otc dgnd1 ognd v ccd1 v cco clk ognd clkn v cco ir dgnd1 ccs 014aaa431 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24 fig 2. pin configuration 6.2 pin description table 2. pin description symbol pin type [1] description n.c. 1 - not connected agnd1 2 g analog ground 1 in 3 i analog input voltage cmadc 4 o regulator common mode adc output inn 5 i complementary analog input voltage agnd1 6 g analog ground 1 dec 7 i/o decoupling node n.c. 8 - not connected fsout 9 o full-scale reference voltage output fsin 10 i full-scale reference voltage input n.c. 11 - not connected n.c. 12 - not connected n.c. 13 - not connected del1 14 i complete conversion signal delay input 1 del0 15 i complete conversion signal delay input 0 v ccd2 16 p digital supply voltage 2 (5.0 v)
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 4 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling [1] p: power supply; g: ground; i: input; o: output. dgnd2 17 g digital ground 2 ce_n 18 i chip enable input (cmos level; active low) otc 19 i control input for two?s comple ment output (active high) ognd 20 g data output ground v cco 21 p data output supply voltage (3.3 v) ognd 22 g data output ground v cco 23 p data output supply voltage (3.3 v) ir 24 o in-range output d11 25 o data output bit 11 (most significant bit (msb)) d10 26 o data output bit 10 d9 27 o data output bit 9 d8 28 o data output bit 8 d7 29 o data output bit 7 d6 30 o data output bit 6 d5 31 o data output bit 5 d4 32 o data output bit 4 d3 33 o data output bit 3 d2 34 o data output bit 2 d1 35 o data output bit 1 d0 36 o data output bit 0 (least significant bit (lsb)) ccs 37 o complete conversion signal output dgnd1 38 g digital ground 1 clkn 39 i complementary clock input clk 40 i clock input v ccd1 41 p digital supply voltage 1 (5.0 v) dgnd1 42 g digital ground 1 agnd2 43 g analog ground 2 v cca2 44 p analog supply voltage 2 (5.0 v) v cca1 45 p analog supply voltage 1 (5.0 v) agnd1 46 g analog ground 1 v cca1 47 p analog supply voltage 1 (5.0 v) agnd1 48 g analog ground 1 dgnd exposed die pad g digital ground table 2. pin description ?continued symbol pin type [1] description
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 5 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling 7. limiting values table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cca analog supply voltage [1] ? 0.5 +7.0 v v ccd digital supply voltage [1] ? 0.5 +7.0 v v cco output supply voltage [2] ? 0.5 +5.0 v ? v cc supply voltage difference v cca ? v ccd ? 1.0 +1.0 v v ccd ? v cco ? 1.0 +4.0 v v cca ? v cco ? 1.0 +4.0 v v i(in) input voltage on pin in referenced to agnd 0 v cca + 1 v v i(inn) input voltage on pin inn referenced to agnd 0 v cca + 1 v v i(clk) input voltage on pin clk referenced to dgnd 0 v ccd + 1 v v i(clkn) input voltage on pin clkn referenced to dgnd 0 v ccd + 1 v i o output current - 10 ma t stg storage temperature ? 55 +150 ?c t amb ambient temperature ? 40 +85 ?c t j junction temperature - 150 ?c [1] the supply voltages v cca and v ccd may have any value between ?0.5 v and +7.0 v provided that the su pply voltage differences ? v cc are respected. [2] the supply voltage v cco may have any value between ?0.5 v and +5.0 v provided that the supply voltage dif ferences ? v cc are respected. 8. thermal characteristics table 4. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient [1] 36.2 k/w r th(j-c) thermal resistance from junction to case [1] 14.3 k/w [1] in compliance with jedec test board, in free air.
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 6 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling 9. characteristics table 5. characteristics v cca = 4.75 v to 5.25 v; v ccd = 4.75 v to 5.25 v; v cco = 2.7 v to 3.6 v; agnd and dgnd shorted together; t amb = 40 q c to +85 q c; v i(in) v i(inn) = 0.5 dbfs; v ref(fs) = v cca 1.87 v; v i(cm) = v cca 1.95 v; typical values measured at v cca = v ccd = 5 v, v cco = 3.3 v, t amb = 25 q c and c l = 10 pf; unless otherwise specified. symbol parameter conditions min typ max unit supplies v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output supply voltage 2.7 3.3 3.6 v i cca analog supply current - 120 135 ma i ccd digital supply current - 50 65 ma i cco output supply current f clk = 80 mhz; f i = 93 mhz - 10 15 ma p tot total power dissipation f clk = 80 mhz; dc input - 840 990 mw clock inputs: pins clk and clkn [1] v il low-level input voltage referenced to dgnd; v ccd = 5 v positive emitter-coupled logic (pecl) mode 3.19 - 3.52 v transistor-transistor logic (ttl) mode dgnd - 0.8 v v ih high-level input voltage referenced to dgnd; v ccd = 5 v pecl mode 3.83 - 4.12 v ttl mode 2.0 - v ccd v i il low-level input current v clk or v clkn = 3.52 v [2] - - 28 p a v clk or v clkn = 0.80 v 1 - - na i ih high-level input current v clk or v clkn = 3.83 v - - 30 p a v clk or v clkn = 2.00 v 2 - - na v i(clk)dif differential clock input voltage v clk v clkn ; ac mode; dc voltage level is 2.5 v 1.3 1.5 1.7 v r i input resistance f clk = 80 mhz [2] - 6.3 - k : c i input capacitance f clk = 80 mhz [2] - 1.1 - ff analog inputs: pins in and inn i il low-level input current v ref(fs) = v cca 1.75 v - 5 - p a i ih high-level input current v ref(fs) = v cca 1.75 v - 5 - p a r i input resistance [2] 6.3 - - m : c i input capacitance [2] - - 700 ff v i(cm) common-mode input voltage v i(in) = v i(inn) ; output code = 2 047 v cca 2 v cca 1.8 v cca 1.6 v digital inputs: pins otc and ce_n v il low-level input voltage dgnd - 0.3 u v ccd v v ih high-level input voltage 0.7 u v ccd - v ccd v
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 7 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling i il low-level input current v il = 0.8 v - 1 - p a i ih high-level input current v ih = 2.0 v - 1 - p a digital inputs: pins del0 and del1 v il low-level input voltage dgnd - 0.3 u v ccd v v ih high-level input voltage 0.7 u v ccd - v ccd v i il low-level input current v il = 0.8 v - 8 - p a i ih high-level input current v ih = 2.0 v - 20 - p a voltage controlled regulator output: pin cmadc v o(cm) common-mode output voltage i l = 0 ma - v cca 1.88 - v i l = 2 ma - v cca 1.95 - v reference voltage input: pin fsin [3] v ref(fs) full-scale reference voltage - v cca 1.80 - v i ref(fs) full-scale reference current - 0.1 - p a v i(a)(p-p) peak-to-peak analog input voltage see figure 5; v i = v i(in) v i(inn) ; v i(cm) = v cca 1.95 v - 1.85 - v full-scale voltage controlled regulator output: pin fsout v o(ref) reference output voltage i l = i ref(fs) - v cca 1.80 - v i l = 2 ma - v cca 1.82 - v digital outputs: pins d11 to d0, ir and ccs output levels v ol low-level output voltage i ol = 2 ma dgnd - dgnd + 0.5 v v oh high-level output voltage i oh = 0.4 ma v cco 0.5 - v cco v i oz off-state output current output level between 0.5 v and v cco 0.1 0 +0.1 p a timing [4] t d(s) sampling delay time c l = 10 pf - 0.1 0.24 ns t h(o) output hold time c l = 10 pf 2.6 3.8 - ns t d(o) output delay time c l = 10 pf - 4.7 7.8 ns 3-state output delay t dzh float to active high delay time - 3.6 - ns t dzl float to active low delay time - 3.9 - ns t dhz active high to float delay time - 9.2 - ns t dlz active low to float delay time - 7.2 - ns table 5. characteristics ?continued v cca = 4.75 v to 5.25 v; v ccd = 4.75 v to 5.25 v; v cco = 2.7 v to 3.6 v; agnd and dgnd shorted together; t amb = 40 q c to +85 q c; v i(in) v i(inn) = 0.5 dbfs; v ref(fs) = v cca 1.87 v; v i(cm) = v cca 1.95 v; typical values measured at v cca = v ccd = 5 v, v cco = 3.3 v, t amb = 25 q c and c l = 10 pf; unless otherwise specified. symbol parameter conditions min typ max unit
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 8 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling clock timing inputs: pins clk and clkn g duty cycle f clk = 80 mhz; f i = 175 mhz 45 - 55 % f clk(min) minimum clock frequency - - 9.5 mhz f clk(max) maximum clock frequency g = 45 % to 55 % 80 - - mhz timing complete conversion signal: pin ccs; see figure 6 t d(ccs) ccs delay time c l = 10 pf; del0 = high; del1 = low - 0.3 - ns c l = 10 pf; del0 = low; del1 = high - 1.3 - ns c l = 10 pf; del0 = high; del1 = high - 2.3 - ns analog signal processing (clock duty cycle 50 %) inl integral non-linearity f clk = 20 mhz; f i = 21.4 mhz - r 2.0 - lsb dnl differential non-linearity f clk = 20 mhz; f i = 21.4 mhz; no missing code guaranteed - r 0.6 - lsb e offset offset error v cca = v ccd = 5 v; v cco = 3.3 v; t amb = 25 q c; output code = 2 047 4 +8 +24 mv e g gain error v cca = v ccd = 5 v; v cco = 3.3 v; t amb = 25 q c - 2.5 - %fs b bandwidth f clk = 80 mhz; 3 db; full-scale input [5] 320 375 - mhz d 2h second harmonic level f i = 21.4 mhz - 79 - dbc f i = 93 mhz - 78 - dbc f i = 175 mhz - 74 - dbc d 3h third harmonic level f i = 21.4 mhz - 84 - dbc f i = 93 mhz - 80 - dbc f i = 175 mhz - 76 - dbc thd total harmonic distortion f i = 21.4 mhz [6] - 75 - dbc f i = 93 mhz - 73 - dbc f i = 175 mhz - 68 - dbc n th(rms) rms thermal noise v i(in) = v i(inn) ; f clk = 80 mhz - 0.45 - lsb table 5. characteristics ?continued v cca = 4.75 v to 5.25 v; v ccd = 4.75 v to 5.25 v; v cco = 2.7 v to 3.6 v; agnd and dgnd shorted together; t amb = 40 q c to +85 q c; v i(in) v i(inn) = 0.5 dbfs; v ref(fs) = v cca 1.87 v; v i(cm) = v cca 1.95 v; typical values measured at v cca = v ccd = 5 v, v cco = 3.3 v, t amb = 25 q c and c l = 10 pf; unless otherwise specified. symbol parameter conditions min typ max unit
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 9 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling [1] the circuit has two clock inputs: clk and clkn. there are 5 modes of operation: a) pecl mode 1: (dc levels vary 1:1 with v ccd ) clk and clkn inputs are at differential pecl levels. b) pecl mode 2: (dc levels vary 1:1 with v ccd ) clk input is at pecl level and sampling is taken on the falling edge of the clock input signal. a dc level of 3.65 v has to be applied on clkn decoupled to gnd via a 100 nf capacitor. c) pecl mode 3: (dc levels vary 1:1 with v ccd ) clkn input is at pecl level and sampli ng is taken on the rising edge of the clock input signal. a dc level of 3.65 v has to be applied on clk decoupled to gnd via a 100 nf capacitor. d) differential ac driving mode 4: when driving the clk input directly and with any ac signal of minimum 1 v (p-p) and with a dc level of 2.5 v, the sampling takes place at the falling edge of the clock si gnal. when driving the clkn input with the same signal, sampling takes place at the rising edge of the clock signal. it is re commended to decouple the clkn or clk input to dgnd via a 100 nf capacitor. e) ttl mode 5: clk input is at ttl level and sampling is taken on the fal ling edge of the clock input signal. in that case clkn pin has to be connected to the ground. [2] guaranteed by design. [3] the adc input range can be adjusted with an external reference connected to pin fsin. this voltage has to be referenced to v cca. [4] output data acquisition: the output data is available after the maximum delay of t d(o) . [5] the 3 db analog bandwidth is determined by the 3 db reduction in the reconstructed output, the input being a full-scale sine wave. [6] the total harmonic distortion is obtained wi th the addition of the first five harmonics. [7] the signal-to-noise ratio takes in to account all harmonics above five and noise up to nyquist frequency. [8] intermodulation measured relative to either tone with analog input frequencies f i 1 and f i 2. the two input signals have the same amplitude and the total amplitude of both signal s provides full-scale to the converter ( 6 db below full-scale for each input signal). imd3 is the ratio of the rms value of either input tone to the rm s value of the worst case third order intermodulation product; imd2 is the ratio of the rms value of either input tone to the rms value of the worst case second order intermodulation product. s/n signal-to-noise ratio f i = 21.4 mhz [7] - 67.4 - dbc f i = 93 mhz 63 67.2 - dbc f i = 175 mhz - 66.5 - dbc sfdr spurious free dynamic range f i = 21.4 mhz - 76 - dbc f i = 93 mhz 68 78 - dbc f i = 175 mhz - 74 - dbc acpr adjacent channel power ratio f i = 93 mhz; 5 mhz channel spacing; b = 3.84 mhz - 70 - db imd2 second-order intermodulation distortion f i 1 = 21 mhz; f i 2 = 22 mhz [8] - 89 - dbfs f i 1 = 91.5 mhz; f i 2 = 94.5 mhz - 86 - dbfs f i 1 = 174 mhz; f i 2 = 176 mhz - 83 - dbfs imd3 third-order intermodulation distortion f i 1 = 21 mhz; f i 2 = 22 mhz [8] - 88 - dbfs f i 1 = 91.5 mhz; f i 2 = 93.5 mhz - 82 - dbfs f i 1 = 174 mhz; f i 2 = 176 mhz - 83 - dbfs table 5. characteristics ?continued v cca = 4.75 v to 5.25 v; v ccd = 4.75 v to 5.25 v; v cco = 2.7 v to 3.6 v; agnd and dgnd shorted together; t amb = 40 q c to +85 q c; v i(in) v i(inn) = 0.5 dbfs; v ref(fs) = v cca 1.87 v; v i(cm) = v cca 1.95 v; typical values measured at v cca = v ccd = 5 v, v cco = 3.3 v, t amb = 25 q c and c l = 10 pf; unless otherwise specified. symbol parameter conditions min typ max unit
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 10 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling 10. additional information relating to table 5 table 6. output coding with differential inputs v i(in) ? ? code v i(in) (v) v i(inn) (v) ir binary outputs (d11 to d0) two?s complement outputs (d11 to d0) underflow < 2.675 > 3.625 0 0000 0000 0000 1000 0000 0000 0 2.675 3.625 1 0000 0000 0000 1000 0000 0000 1 - - 1 0000 0000 0001 1000 0000 0001 ? ? ? ? ? ? 2 047 3.15 3.15 1 0111 1111 1111 1111 1111 1111 ? ? ? ? ? ? 4 094 - - 1 1111 1111 1110 0111 1111 1110 4 095 3.625 2.675 1 1111 1111 1111 0111 1111 1111 overflow > 3.625 < 2.675 0 1111 1111 1111 0111 1111 1111 table 7. mode selection two?s complement output (otc) chip enable input (ce_n) data output (d0 to d11; ir) 0 0 binary; active 1 0 two?s complement; active x [1] 1 high-impedance [1] x = don?t care. in clk 0.5 v n d0 to d11 v cco ? 0.5 v 50 % data n ? 1 data n data n + 1 t d(o) t d(s) t h(o) 014aaa432 sample n sample n + 1 sample n + 2 sample n + 3 sample n + 4 fig 3. output timing diagram
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 11 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling f i (mhz) 0 40 30 20 10 014aaa435 ?80 ?120 ?40 0 power spectrum (dbc) ?160 (1) (5) (6) (4) (3) (2) (1) f i 1h = 15 mhz; 0 dbc (2) f i 2h = 5.1 mhz; ?79.6 dbc (3) f i 3h = 9.88 mhz; ?82.1 dbc (4) f i 4h = 20.1 mhz; ?80.6 dbc (5) f i 5h = 30 mhz; ?74.7 dbc (6) f i 6h = 35.1 mhz; ?93.9 dbc thd (5h): ?72.2 dbc sfdr: 74.7 dbc fig 4. single tone; f i = 175 mhz; f clk = 80 mhz v ref(fs) (v) 1.4 2.2 2.0 1.8 1.6 014aaa436 1.8 1.6 2.0 2.2 v i(a)(p-p) (v) 1.4 fig 5. adc full-scale; v i(a)(p-p) as a function of v ref(fs) the ADC1207S080 allows modi fying the adc full-scale. th is could be done with fsin (full-scale input) according to figure 5.
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 12 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling the ADC1207S080 generates an adjustable clock output called complete conversion signal (ccs), which can be used to control th e acquisition of converted output data by the digital circuit connected to the ADC1207S080 output data bus. two logic inputs, del0 and del1 pins, allow adjusting the delay of the edge of the ccs signal to achieve an optimal position in the stable, usable zone of the data. table 8. complete conver sion signal selection del1 del0 ccs output 0 0 high-impedance 0 1 active, typical delay 0.3 ns 1 0 active, typical delay 1.3 ns 1 1 active, typical delay 2.3 ns 014aaa433 d0 to d11 (1) ccs t d(ccs) (1) t d(css) is referenced to the middle of the active data. fig 6. complete conversion signal timing diagram
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 13 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling 11. definitions 11.1 static parameters 11.1.1 integral non-linearity (inl) it is defined as the deviation of the transfer f unction from a best fit straight line (linear regression computation). the inl of the code i is obtained from the equation: inl i ?? v i i ?? v i ideal ?? ? s ----------------------------------------- = where: s corresponds to the slope of the ideal straight line (code width); i corresponds to th e code value; v i is the input voltage. 11.1.2 differential non-linearity (dnl) it is the deviation in code width from the value of 1 lsb. dnl i ?? v i i1 + ?? v i i ?? ? s -------------------------------------- - = where: v i is the input voltage; i from 0 to (2 n ? 2). 11.2 dynamic parameters figure 7 shows the spectrum of a single tone fu ll- scale input sine wave with frequency f, conforming to coherent sampling (f/f s = m/n, with m number of cycles and n number of samples, m and n being relatively prime), and digitized by the adc under test. a 2 a 1 magnitude frequency 014aaa437 sfdr a k s a 3 fig 7. single tone spectrum of full-scale input sine wave with frequency f t
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 14 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling remark: in the following equations, p noise is the power of the terms which include the effects of random noise, non-linearities, sampling time errors, and ?quantization noise?. 11.2.1 signal-to-noise and distortion (sinad) the ratio of the output signal power to the noi se p lus distortion power for a given sample rate and input frequency, excluding the dc component: sinad db ?? 10log 10 p signal p noise distortion + --------------------------------------- - ?? ?? = 11.2.2 effective number of bits (enob) it is derived from sinad and gives the theoretical resolution an ideal adc would require to obtain the same sinad measured on the real adc. a good approximation gives: enob sinad 1.76 ? 6.02 ---------------------------------- = 11.2.3 total harmonic distortion (thd) the ratio of the power of the harmonics to the power of the fundamental. for k ? 1 h armonics the thd is: thd db ?? 10log 10 p harmonics p signal ------------------------- ?? ?? = where: p harmonics ? 2 2 ? 3 2 ?? k 2 +++ = p signal ? 1 2 = the value of k is usually 6 (i.e. calculation of thd is done on the first 5 harmonics). 11.2.4 signal-to-noise ratio (s/n) the ratio of the output signal power to the noise power, excluding the harmonics and the dc component is: sn ? db ?? 10log 10 p signal p noise ---------------- ?? ?? = 11.2.5 spurious free dynamic range (sfdr) the number sfdr specifies available signal ra n ge as the spectral distance between the amplitude of the fundamental and the amplit ude of the largest spurious harmonic and non-harmonic, excluding dc component: sfdr db ?? 20log 10 ? 1 max s ?? ------------------ ?? ?? =
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 15 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling 11.2.6 imd2 (imd3) f 1 ? f 2 2f 2 ? f 1 2f 1 ? f 2 f 1 + f 2 2f 2 2f 1 f 2 f 1 f 1 + 2f 2 3f 2 2f 1 + f 2 3f 1 magnitude frequency 014aaa439 fig 8. spectral of dual tone input sine wave with frequency from a dual tone input sinusoid (f t1 and f t2 , these frequencies being chosen according to the coherence criterion), the intermodulation distortion products imd2 and imd3 (respectively, 2nd and 3rd order components) are defined, as follows. the ratio of the rms value of either tone to the rms value of the worst second (third) order intermodulation product. the total intermodulation distortion (imd) is given by: imd db ?? 10log 10 p intermod p signal ---------------------- ?? ?? = where: p intermod ? im f t1 f t2 ? ?? 2 ? im f t1 f t2 + ?? 2 ? ? im f t1 2f t2 ? ?? 2 ? im f t1 2f t2 + ?? 2 ? +++ = ?? + im 2f t1 f t2 ? ?? 2 ? im 2f t1 f t2 + ?? 2 + with ? im f t1 ?? 2 corresponding to the power in the intermodulation component at frequency f t . p signal ? f t1 2 ? f t2 2 +=
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 16 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling 12. application information 12.1 ADC1207S080 in 3g radio receivers the ADC1207S080 has been proven in many 3g radio receivers with various operating conditions regarding input frequency (if), signal if bandwidth and sampling frequency. the ADC1207S080 is provided with a maximum analog input signal frequency of 400 mhz. it allows a significant cost-down of th e rf front-end, from two mixers to only one, even in multi-ca rriers architecture. ta b l e 9 describes some possible applications wit h the ADC1207S080 in high if sampling mode. table 9. examples of possible f i , f clk , if bw combinations supported f i (mhz) f clk (mhz) if bw (mhz) [1] snr (db) sfdr (dbc) 350 80 5.00 65 71 243.95 9.60 0.25 71 80 96 76.80 1.60 72 76 96 76.80 4.80 71 77 96 76.80 20.00 68 76 80 61.44 10.00 70 85 78.4 44.80 3.50 71 76 70 40.00 1.25 72 79 [1] if bandwidth corresponds to the observed area on the adc output spectrum. for a dual carrier wideband-code-division-mult iple-access (w-cdma) receiver, the most important parameters are se nsitivity and adjacent chann el selectivity (acs). the sensitivity is defined as the lo west detectable signal level. in w-cdma, it can be far below the noise floor. this difference , between the sensitivity and t he noise floor, is defined by the sensitivity-to-noise ratio (senr). its valu e is negative due to the gain processing. the adjacent channel power ratio (acpr) is the difference between the full-scale ? 3 db p eak and the noise floor. it represents t he ratio of the adjacent-channel power and the average power level of the channel. the acs is defined by the sum of senr and acpr. 014aaa434 acpr nf interfering channel wanted channel acs noise floor sensibility thermal noise senr fig 9. adjacent channel sens itivity and adc sensibility
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 17 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling 12.2 application diagram 014aaa438 36 ADC1207S080 dgnd 35 d0 d1 34 d2 33 d3 32 d4 31 d5 30 d6 29 d7 28 d8 27 d9 26 d10 25 d11 37 ccs 38 dgnd1 39 clkn 40 clk v ccd1 4142 dgnd1 43 agnd2 44 v cca2 45 v cca1 46 agnd1 47 v cca1 48 agnd1 4 cmadc 5 inn 6 agnd1 7 dec 8 n.c. 9 fsout 10 fsin 11 n.c. 12 n.c. 242322212019181716151413 ir v cco ognd v cco ognd otc ce_n dgnd2 v ccd2 del0 del1 n.c. v ccd 330 nf 100 nf 4700_000_s (16) (41) (44) (45) (47) (21) (23) 10 nf 10 nf v cca 330 nf 100 nf 4700_000_s hf70acb 10 nf out adj v cco 100 nf 10 nf 10 nf in 32 1 lm317mdt 300 240 4.7 f 470 nf 10 v 5 v gnd analog ground 1 2 n.c. agnd1 v cca v ccd n.c. 100 nf 100 nf clk tl431cpk adt1_1wt v ccd1 3 5 1 6 2 4 50 v ccd v cco g1 3 in in 10 nf 10 nf digital ground 2 4 6 10 nf 10 nf 330 nf 100 100 2.2 k adt1_1wt 3 1 5 100 nf 100 nf n.c. xx xx fig 10. application diagram
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 18 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling 13. package outline unit a max. a 1 a 2 a 3 b p h d h e l p z d (1) z e (1) ce ly wv references outline version european projection issue date iec jedec jeita mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 7.1 6.9 0.5 9.1 8.9 0.9 0.6 7 0 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot545-2 ms-026 03-04-07 04-01-29 d (1) e (1) 7.1 6.9 9.1 8.9 d h e h 4.6 4.4 4.6 4.4 0.9 0.6 b p e e a 1 a l p detail x l b 12 1 48 37 d h b p e h a 2 v m b d z d a c z e e v m a x 25 36 24 13 y pin 1 index w m w m 0 2.5 5 mm scale htqfp48: plastic thermal enhanced thin quad flat package; 48 leads; body 7 x 7 x 1 mm; exposed die pad sot545-2 d h e h exposed die pad side (a ) 3 fig 11. package outline sot545-2 (htqfp48)
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 19 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling 14. revision history table 10. revision history document id release date data sheet status change notice supersedes ADC1207S080_3 20120702 product data sheet - ADC1207S080_2 ADC1207S080_2 20080807 product data sheet - ADC1207S080_1 modifications: corrections made to version number in table ? 1. corrections made to several entries in table ? 5. corrections made to alignment in figure ? 10. corrections made to figure ? 11. ADC1207S080_1 20080611 product data sheet - - 15. contact information for more information or sales office addresses, please visit: http://www.idt.com
ADC1207S080_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 20 of 20 integrated device technology ADC1207S080 single 12 bits adc, up to 80 mhz with direct/ultra high if sampling 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 thermal characteristics . . . . . . . . . . . . . . . . . . 5 9 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 10 additional inform ation relating to table 5 . . . 10 11 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 11.1 static parameters . . . . . . . . . . . . . . . . . . . . . . 13 11.1.1 integral non-linearity (inl) . . . . . . . . . . . . . . 13 11.1.2 differential non-linearity (dnl) . . . . . . . . . . . 13 11.2 dynamic parameters . . . . . . . . . . . . . . . . . . . 13 11.2.1 signal-to-noise and dist ortion (sinad) . . . . 14 11.2.2 effective number of bits (enob) . . . . . . . . . 14 11.2.3 total harmonic distortion (thd) . . . . . . . . . . 14 11.2.4 signal-to-noise ratio (s/n) . . . . . . . . . . . . . . . 14 11.2.5 spurious free dynamic range (sfdr). . . . . 14 11.2.6 imd2 (imd3) . . . . . . . . . . . . . . . . . . . . . . . . . 15 12 application information . . . . . . . . . . . . . . . . . 16 12.1 ADC1207S080 in 3g radio receivers. . . . . . . 16 12.2 application diagram . . . . . . . . . . . . . . . . . . . . 17 13 package outline. . . . . . . . . . . . . . . . . . . . . . . . 18 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 19 15 contact information . . . . . . . . . . . . . . . . . . . . 19 16 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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